Creating your own RISC-V processor, SoC and board with Claude

A write-up on cimons.com, Creating your own RISC-V processor, SoC and board with Claude, describes building a custom RISC-V CPU, system-on-chip, and physical board with help from Claude. The piece is listed under HN Claude/Codex/Fable and has a Hacker News thread at item id 49015255 with 3 points and 1 comment.

The work spans three layers that usually stay separate: a RISC-V processor core, an SoC that wraps that core with the rest of the chip, and a board that brings the silicon into a usable hardware product. Claude is used across that path, so the article is less a single RTL snippet and more an end-to-end design narrative from ISA-facing logic down to board bring-up.

For engineers and builders, the useful signal is the full stack in one project. Most hobby or education efforts stop at a soft core in an FPGA or at a pre-made SoC module. Documenting processor, SoC, and board together shows where LLM assistance can help with specification, HDL-style structure, integration choices, and board-level decisions without claiming it replaces silicon process knowledge or lab validation.

In competitive and market terms, RISC-V is the open ISA path many teams use when they want a custom core without an Arm license. Pairing that with Claude puts this in the same lane as other Claude/Codex-style tooling write-ups on HN: AI as a design co-pilot for hardware, not only for software. The low early score (3 points, 1 comment) means the thread is still thin; the durable value is the article itself, not community consensus yet.

Practical takeaway: treat the post as a map of the full RISC-V product stack (core → SoC → board) and as a worked example of where Claude sits in that workflow. What to watch next is whether follow-ups publish concrete artifacts people can inspect or reuse—core sources, SoC block diagrams, board files—and whether the HN discussion grows past the current 3-point, 1-comment snapshot.