TB
Tech Bytes
Silicon Architecture • Source: Ars Technica • August 21, 2026

Deep-Dive: Etched Sohu ASIC Microarchitecture & Rack Power

Deep-Dive: Etched Sohu ASIC Microarchitecture & Rack Power

An architectural deep-dive into how Etched Sohu ASIC hardwires transformer attention into custom silicon, drastically reducing memory bandwidth constraints.

Eliminating Instruction Fetch overhead in Transformer Kernels

Underlying the Etched Sohu processor is an uncompromising silicon design philosophy: eliminate the general-purpose SIMD execution pipelines found in standard GPUs. By replacing flexible CUDA cores with dedicated matrix-multiplication blocks and hardwired Softmax/LayerNorm pipelines, the chip avoids dynamic instruction decoding overhead during inference.

Stay Ahead in Tech

Get the Daily Tech Bytes Briefing

Join 45,000+ engineers, founders, and tech leaders receiving high-signal analysis directly to their inbox every morning.

Rack-Scale Optical Interconnects and Liquid Cooling Integration

Sohu pairs its custom logic cores with a massive 144MB ultra-fast SRAM buffer directly adjacent to the compute units, backed by HBM3e stacks. This hybrid memory hierarchy ensures KV-cache tokens remain in high-speed local memory during long-context generation, preventing memory bus saturation during multi-turn conversational requests.

At the rack scale, Etched employs direct-to-chip liquid cooling plates and co-packaged optical interconnects. This design enables 32-node racks to function as a single logical inference domain, achieving microsecond inter-chip communication without Ethernet packet overhead.

TB
Tech Bytes Editorial
Published August 21, 2026
← Back to Today's Tech Pulse