Epic Microsystems has raised $21M to commercialize vertical power delivery for AI racks. Learn about Hybrid Switched-Capacitor (HSC) architecture and 100kW+...
The 100kW+ Rack Problem
As AI accelerators pack more compute into every rack, the power a single rack must absorb has climbed past 100kW. The bottleneck is no longer generating that power upstream — it is getting it the last few inches to the chips without losing a large share of it to resistance along the way. When current is high and voltage at the load is low, even short copper paths turn into significant heat and voltage droop.
Traditional power delivery routes current laterally across the board before it reaches the processor, forcing it through connectors, planes, and traces that add resistance at exactly the point where losses hurt most. At rack densities measured in the tens of kilowatts and beyond, that lateral path becomes the wall that limits how much compute you can actually feed.
What Vertical Power Delivery Changes
Vertical power delivery flips the geometry. Instead of pushing current across the plane and then up into the package, conversion is moved directly beneath the load so power flows straight up into the chip. Shortening that final path cuts the resistive losses and the voltage drop that scale with current, which is the term that dominates at high amperage.
The practical payoff is more usable power at the die for the same input, and less waste heat generated right next to the components that are already the hardest to cool. It also frees board area on the top side of the package, since the bulky conversion stage no longer has to sit beside the processor and compete for space and routing.
Hybrid Switched-Capacitor Architecture
Epic Microsystems is building this around a Hybrid Switched-Capacitor (HSC) architecture. Switched-capacitor conversion moves energy using capacitors and switches rather than relying primarily on magnetics, which lets the converter shrink and sit closer to the load. The hybrid part combines that capacitor-based stage with an inductive element so the design keeps tight regulation while still converting a large voltage ratio efficiently.
That combination matters for AI racks specifically, where the goal is to step a higher distribution voltage down to the low core voltage a processor needs, at very high current, in a footprint small enough to place vertically under the die. The things this architecture is trying to balance are worth calling out plainly:
- High conversion ratio from distribution voltage down to core voltage
- Small physical footprint so the stage fits beneath the load
- Tight output regulation despite fast, large current swings
- High efficiency to limit added heat at the densest point in the rack
Why the $21M and the Timing
Epic Microsystems raised $21M to commercialize this approach, which signals that the work has moved past proving the concept and toward productizing it for real racks. Turning a power-conversion architecture into shipping silicon means building the parts, qualifying them, and integrating them with the packaging and board designs that accelerator vendors already use — none of which is trivial at these current levels.
For teams planning high-density AI infrastructure, the takeaway is to treat last-inch power delivery as a first-class design constraint rather than an afterthought. Where the conversion stage physically sits, and how short the path from converter to die is, increasingly determines how much compute a rack can sustain before power and thermal limits, not the silicon itself, cap performance.