Claude designed FPGA scaler board for 6th-gen consoles

Open-source developer bryfur released the tang-av-scaler revision C-B board, an FPGA video processor that converts 480i component video and analog stereo audio from sixth-generation consoles into 1080p60 HDMI with two milliseconds of delay. As detailed in github.com's report, the board couples dedicated analog decoders with a Gowin GW5AST-138 gate array to upscale retro hardware signals. A custom carrier board hosts the module alongside a Wi-Fi microcontroller for wireless management.

This breakdown covers the board's processing logic, spatial reconstruction algorithms, embedded RISC-V architecture, measured performance metrics, and current hardware constraints. It is tailored for retro gaming enthusiasts, FPGA designers, and hardware engineers evaluating real-time upscaling options. Readers will find exact technical specifications for video deinterlacing, memory routing, and system clock synchronization.

01Signal capture and motion adaptive deinterlacing

Video enters through an Analog Devices ADV7181D decoder sampled line-locked at 13.5 MHz, while a PCM1808 converter digitizes stereo analog audio. The decoder sampling phase can be automatically tuned across a still frame to match console pixel timing. Captured fields stream directly into DDR3 memory on the system-on-module for temporal processing.

Deinterlacing uses a motion-adaptive algorithm referencing the four most recent fields in DDR3 storage. The logic passes stationary lines from the prior field while interpolating moving areas from adjacent vertical scanlines. Users can also select standard bob or weave deinterlacing through configuration settings.

Temporal noise reduction averages stationary pixel samples with those from the preceding frame across three user-selectable strengths. The pipeline also measures dark borders around active game visuals, cropping blank canvas space so graphics fill modern displays. These border offsets can alternatively be adjusted manually when required.

02Edge adaptive upscaling and spatial sharpening

Anti-aliasing across the 480-line progressive frame relies on Subpixel Morphological Anti-Aliasing at 1x strength. The algorithm evaluates luminance edges to identify orthogonal and diagonal patterns while maintaining corner fidelity. An integrated diagnostic mode paints edge maps directly onto the video output to assist threshold calibration.

Upscaling employs AMD FidelityFX Super Resolution edge-adaptive spatial upsampling to expand frames into standard high-definition formats. Content scales to 1440 by 1080 pixels for 4:3 titles or 1920 by 1080 pixels for games supporting 16:9 widescreen presentation. The processing runs directly in logic at a 148.5 MHz output pixel clock.

Following upsampling, Robust Contrast Adaptive Sharpening processes the luminance channel across sixteen discrete intensity steps. An integrated noise term prevents the filter from exaggerating background noise in flat image areas. The scaled frame then merges with an on-screen telemetry overlay before digital serialization.

03System on module architecture and wireless control

The hardware core is a Sipeed Tang Mega 138K module carrying a Gowin GW5AST-138 FPGA. The entire video processing pipeline is synthesized in register-transfer logic simulated against bit-accurate Python reference models. The active gateware consumes sixteen percent of logic elements, seventy-five percent of block RAM, and fifteen percent of multipliers.

Control tasks run bare-metal on an integrated Andes A25 32-bit RISC-V hard processor core. This core brings up peripheral silicon, calculates display borders, optimizes sampling phases, and coordinates output frame timing. Updated control software loads into the processor in one second without regenerating FPGA bitstreams.

A Seeed Studio XIAO ESP32-C5 module handles wireless networking, user interfaces, and non-volatile configuration storage. The ESP32 communicates with the RISC-V processor over SPI and hosts an embedded web portal for real-time adjustments. It provides remote firmware updating and exposes a wireless JTAG interface for gateware loading.

04Measured processing latency and frame lock performance

Direct board measurements indicate a processing delay of 2.0 milliseconds at the top of the video raster. Differences between input and output refresh rates push latency to 2.5 milliseconds at the bottom of the frame, contrasting with 16.8 milliseconds for full-field buffering. Latency is tracked internally from line arrival to HDMI dispatch.

The RISC-V processor synchronizes output frames with input fields by trimming the clock generator frequency. Tested against a PlayStation 2 console, the system pulled the clock by -57 parts per million to maintain lock within ten microseconds. The control loop reached synchronization within twenty seconds after starting five milliseconds apart.

Noise spread in flat image areas measured 2.32 raw, falling to 1.98 with noise reduction active. Maximum sharpening raised noise to 3.94, while the adaptive noise limiter contained it to 3.12, reaching 2.61 with both active. Remote frame captures transmit over the web portal in two to six seconds.

05Platform compatibility limits and power cycle quirks

Hardware validation has focused solely on the Sony PlayStation 2, though Microsoft Xbox and Nintendo GameCube systems share identical 480i component electrical characteristics. Physical connectors for S/PDIF, VGA, and RGB with SCART sync exist on the board but lack driver support. Resolutions beyond 480i also require new decoder profiles.

The FPGA transceivers feed a Texas Instruments SN65DP159 retimer to produce 1080p60 HDMI video with 48 kHz stereo audio. External displays accept 2160p30 test patterns cleanly, but 2160p60 link negotiations produce scrambled signaling without picture. The internal scaling architecture terminates at 1080p resolutions for monitors, capture devices, and receivers.

Cold boots encounter a clock initialization bug where an unaligned transceiver lane forces the ESP32 to trigger an automatic reload, causing a twenty-second startup delay. In addition, direct bitstream programming into SRAM over Wi-Fi causes unhandled microcontroller restarts, making USB-based JTAG flashing the only reliable method for testing new gateware builds.