Scrying the AMD GFX1250 LLVM Tea Leaves

LLVM commits reveal AMD's GFX1250 (MI455X) as a pure-compute ML accelerator that drops graphics hardware entirely.

What the LLVM commits reveal

GFX1250 is AMD's MI455X accelerator aimed at machine-learning workloads and powering the Helios rack — a datacenter part, distinct from consumer GPUs.

It runs exclusively in Wave32 mode (unlike RDNA's Wave32/Wave64 split) and supports 20 waves per SIMD, up from RDNA4's 16.

Registers, memory and tensors

VGPRs expand to 1,024 per wave, against 512 on prior CDNA and 256 on RDNA. Local memory is addressable up to 320kB per wavefront — twice CDNA4 — via a merged 448KB WGP cache that folds LDS and vector L0 into one structure.

WMMA support pairs RDNA4's programming model with CDNA4's performance, covering all CDNA4 and RDNA4 datatypes except fp64 (reserved for GFX1251), and adds OCP MX-style scaling previously exclusive to CDNA4.

Built for accelerators, not frames

New capabilities include cluster-level synchronisation for inter-workgroup communication, hardware tanh, cooperative atomics (32x4B, 16x8B, 8x16B), new wait counters (ASYNCcnt, TENSORcnt, Xcnt) and a tensor data mover for direct global-to-LDS transfers.

Most telling: rasterisation, texturing and raytracing instructions are removed entirely. This is a compute part with the graphics pipeline deleted.