Unifying Edge AI: How Coral NPU’s open standard brings portable

The source has no shell installer or price figures, so the how-to blocks and the before/after table will use only the published toolchain, boards, and measured deltas. I'll count words and the deck length before the article is final.Google Research has completed the 32-bit Coral NPU, an open ML-first RISC-V design, and released Coral Compiler v1.0 with it. Billy Rutledge, engineering director at Google Research, wrote in Google Developers Blog's report on October 20, 2026, that the Matrix Execution Unit is configurable for up to 1 TOPS and targets 10 mW average power for inference. The post unveils the second-generation Synaptics Astra SR200 series at 400 GOPS, the new Coralboard SR, and worldwide DigiKey availability of the Coralboard SL at 1 TOPS.

It is for teams deploying models to wearables, hearables, autonomous robots, and smart sensors, and for custom edge-SoC and ML-compiler engineers. Those devices need low latency, strict privacy, and all-day reliability without a constant cloud round trip. Edge and cloud work as a model cascade: ultra-low-power models sense and respond, then hand off to larger on-device or cloud models. The piece covers the four 32-bit milestones, the IREE/MLIR compiler, the Synaptics boards, and the 64-bit and CHERI follow-on.

What Unifying Edge AI shipped

Milestone 4, the Matrix Execution Unit, completes the 32-bit Coral NPU this month. It follows the RISC-V VME specification in the Zvt family and uses an outer-product MAC engine at 256 MACs per cycle, one 2D tile per cycle, reusing weights and activations in local registers. That is quadratic throughput, up to 1 TOPS, in a sub-10 mW envelope. Milestone 1 is a C-programmable RISC-V scalar frontend, Milestone 2 an RVV v1.0 vector co-processor, and Milestone 3 a tightly coupled memory subsystem with floating-point support. The RTL is on GitHub.

Coral Compiler v1.0 is the open-source IREE/MLIR toolchain for that RTL. It takes JAX, PyTorch, and TensorFlow through StableHLO and TOSA, partitions the host CPU and the Coral NPU, fuses operators, tiles matrices for local SRAM and matrix accumulators, and emits scalar, RVV v1.0 vector, and VME instructions. The MPACT simulator and a reference FPGA design are for benchmarking and tuning before fabrication. At Synaptics Tech Day on October 20, 2026, Synaptics launched the taped-out Astra SR200 series, Coralboard SR, and Coralboard SL.

What changed for builders in Unifying Edge AI

Google Research introduced Coral NPU last year with the claim that an open hardware and software standard is "the only way to unify the edge and unlock developer productivity and portability." The edge is "split across hundreds of proprietary chip architectures and incompatible toolchains," so teams rewrite kernels, re-quantize models, and debug a vendor compiler per chip. Unsupported layers on peak-compute accelerators fell back to a CPU, hurting latency and battery life. The aim is energy-viable compute: one model across SoC vendors, devices, and power envelopes.

Scalar and vector units stay on control logic and signal processing. Vision encoders and transformer attention are mostly GEMM and GEMV, and a 1D vector engine reloads weights and activations until data movement costs more than the math. A sub-10 mW matrix engine lets a small battery run continuous multimodal models, compact transformers such as Gemma, wearable voice translation, hearable spatial audio, and low-latency robot vision, past keyword spotting and basic motion detection. VeriSilicon is verifying the design for tape-out.

How to install or upgrade Unifying Edge AI

Use the complete 32-bit RTL on GitHub and Coral Compiler v1.0. Bring a JAX, PyTorch, or TensorFlow model through StableHLO and TOSA. IREE/MLIR partitions the host CPU from the Coral NPU, fuses operators, tiles matrices to local SRAM and the matrix accumulators, and emits scalar, RVV v1.0 vector, and VME instructions. Benchmark and tune on the open-source MPACT simulator and the reference FPGA before fabrication. VeriSilicon handles verification, GlobalFoundries supplies the 12LP+ FinFET process, and Grinn is the System-on-Module partner.

JAX or PyTorch or TensorFlow
  -> StableHLO and TOSA
  -> partition: host CPU and Coral NPU core
  -> operator fusion
  -> tile matrices to local SRAM and matrix accumulators
  -> Coral NPU scalar, RVV v1.0 vector, VME matrix instructions
Pre-silicon: MPACT simulator and reference FPGA design
RTL: complete 32-bit Coral NPU on GitHub

Coralboard SR is the new Astra SR200 kit, taped out and launching this month at 400 GOPS, with second-generation Coral NPU IP including Milestone 2 RISC-V Vector Core support. It is an ultra-low-power MCU for battery wearables, industrial sensors, and physical-AI prototypes. Coralboard SL is generally available worldwide through DigiKey after a limited Google I/O preview, with SDKs on the Synaptics Coralboard Developer page. The SL uses the Astra SL2619 and a 1 TOPS Torq / Coral NPU subsystem for multi-stream vision on Linux IoT and robotics.

```text
Coralboard SR
  Silicon: Synaptics Astra SR200 series (taped out, launching this month)
  Compute: 400 GOPS, second-generation Coral NPU IP
  Includes: Milestone 2 RISC-V Vector Core support
  Class: ultra-low-power MCU for wearables and industrial sensor nodes

Coralboard SL Silicon: Synaptics Astra SL2619 Compute: 1 TOPS Torq / Coral NPU subsystem Class: Linux IoT and robotics, transformer and multi-stream vision Status: general availability worldwide through DigiKey Docs: Synaptics Coralboard Developer page ```

Gotchas and compatibility in Unifying Edge AI

Control flow stays on the scalar core, SIMD on the RVV v1.0 co-processor, and GEMM and GEMV on the Matrix Execution Unit via RISC-V VME in the Zvt family. A model that never emits VME instructions misses 256 MACs per cycle and the range up to 1 TOPS, because 2D math on the vector engine reloads weights and activations from memory. The SR200 specifies Milestone 2 vector-core support at 400 GOPS. The 1 TOPS Torq block is the Astra SL2619 on Coralboard SL.

Compiler v1.0 accepts JAX, PyTorch, and TensorFlow through StableHLO and TOSA, and the October 20 post gives no package name or framework version pin. MPACT and the reference FPGA are the pre-silicon benchmark and tuning tools. On GlobalFoundries 12LP+ FinFET, RTL iterations sped core timing by 70% and cut standard-cell area by up to 15%. Ultra-low-power 12LP+ libraries for the matrix unit are still under evaluation. Coralboard SR is the milliwatt MCU kit and Coralboard SL is the 1 TOPS Linux board, on one IREE/MLIR workflow.

What to watch after Unifying Edge AI

The next phase, which Google Research says is already underway, is a 64-bit Coral NPU architecture and CHERI support for security. Still open are VeriSilicon's verification for turnkey tape-outs and GlobalFoundries' evaluation of 12LP+ ultra-low-power libraries for the Matrix Execution Unit. Published 12LP+ FinFET results across RTL iterations show core timing faster by 70% and standard-cell area down by up to 15%. Google invites silicon partners to take the complete open 32-bit RTL, available on GitHub today, into commercial production.

At Synaptics Tech Day on October 20, 2026, the Astra SR200 series is taped out and launching this month at 400 GOPS. Coralboard SR is the new kit for MCU-class edge and physical AI. Coralboard SL is generally available worldwide on DigiKey after the Google I/O preview, with SDKs on the Synaptics Coralboard Developer page. Grinn is the System-on-Module partner from kit to production. The claim to test is one IREE/MLIR workflow for the milliwatt SR board and the 1 TOPS SL board.